The present invention relates to a manufacturing technique of a semiconductor device, particularly to a technique effective when applied to a semiconductor device having a MISFET (metal insulator semiconductor field effect transistor) of the generation of a gate length not greater than 0.1 μm.
As a MISFET capable of controlling short channel effects, a MISFET having a punch through stopper layer of a pocket structure is described in Japanese Patent Application Laid-Open No. Hei 4(1992)-58562.
This MISFET is fabricated by ion-implanting a second conductivity type impurity to the surface of a substrate with a gate electrode, which has been formed over a first conductivity type substrate through an insulating film, as a mask, thereby forming a first diffusion region; ion-implanting a first conductivity type impurity below this first diffusion region, thereby forming a second diffusion region, that is, a so-called punch-through stopper layer having a pocket structure; forming a conductive side wall film on both sides of the gate electrode; and then ion-implanting a second conductivity type impurity into the surface of the substrate with the side wall film and the gate electrode as a mask, thereby forming a third diffusion region.
The short channel effects occur mainly because an electric field generated from the drain of a MISFET reaches the source, thereby causing an electric current to flow between the source and drain. In the above-described MISFET, however, the electric field intensity generated from the drain is suppressed by the punch-through stopper layer (second diffusion region) having a reversal field type pocket structure, making it possible to avoid generation of short channel effects even if the gate length is 0.2 μm or so.